Stacking Faults in 3C-SiC
CHALLENGE project talk at PRIME 2020
Watch the video: https://youtu.be/G3wWfSifKwg
Francesco La Via – CHALLENGE coordinator – was invited to the PRIME 2020 event organized by Electrochemical Society (ECS) with the talk “Stacking Faults in 3C-SiC: From the Crystal Structure to the Electrical Behavior”. CHALLENGE project presents the study on the primary defects of 3C-SiC material. Indeed, the interface between 3C-SiC and Si is the origin of a high density of planar and volume defects, such as micro twins, anti-phase boundaries and stacking faults in the epilayer and voids in Si underneath the hetero-interface. Most of these defects, considered killers for devices, however, reduce their density, and some are annihilated, when very thick (several tens of microns) 3C-SiC epitaxial films are realized.
The primary defects that also remain after the growth of several tens of microns are the Stacking Faults (SFs). We observed three main SFs in 3C-SiC: the intrinsic one where only one plane is shifted concerning the lattice position and two extrinsic SFs where two or three layers are moved. In these last cases, we observe locally the same crystallographic structure of the hexagonal polytypes as in 4H-SiC and 6H-SiC. Recently, a large investigation has been done on these defects to see their crystallographic structure, the interactions between different SFs, the influence of the SFs on the internal stress of the material, the effects of several growth parameters (i.e. temperature, doping, growth rate…) on the density and evolution of these defects. Finally, we carried out several local electrical measurements with C-AFM to understand the defects’ effect on the electrical behaviour of the devices.